Devices including composite thermal capacitors

ABSTRACT

Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of allowed copending U.S.utility application entitled, “Devices Including Composite ThermalCapacitors,” having Ser. No. 13/066,998, filed Apr. 29, 2011, now U.S.Pat. No. 8,378,453 issued Feb. 19, 2013 which is entirely incorporatedherein by reference.

FEDERAL SPONSORSHIP

This invention was made with Government support under Contract/Grant No.HR0011-10-3-0002, awarded by DARPA. The Government has certain rights inthis invention.

BACKGROUND

The exponential growth in the number of on chip transistors so reliablypredicted by Moore's Law has proven to be a powerful driver forincreases in computing performance over the past 40 years, althoughlimitations associated with wire delay, power consumption, and heatgeneration have recently become significant challenges to traditionaltransistor scaling. The desire to maintain the historic rate ofadvancement in the industry, while avoiding the roadblocks associatedwith power consumption and wire delay have led to the consideration ofseveral disruptive design strategies for next generation devicesincluding many core processors and 3D vertical integration.

Pollack's and Amdahl's scaling laws indicate that for power-constrainedchip designs, architectures that implement many simple, low power coresshould maximize the system's overall performance-per-W, as long as thecode is massively parallelizable. To avoid limitations in computationspeed due to the serial portions of the code, asymmetric corearchitectures can be implemented where a few higher power serial coresaugment the performance of the low power cores to provide additionalthroughput. Architectures that vertically integrate the cores in a 3Dmulti-tier package allow for a number of additional design advantages,including shorter wire lengths, increased packaging density, andheterogeneous technology integration that translate into a range ofpotential performance benefits such as decreases in noise, capacitance,and power consumption.

In a many-core system, the thermal profile across the chip can beleveled by actively migrating computations from hotter to cooler areasof the chip, reducing the problem of localized hotspots that have becomeproblematic in modern architectures. While this Dynamic Core Migration(DCM) scheme can mitigate hotspots for most cores, serial cores withtheir potentially higher power densities, larger size, and smallernumber may still experience hotspots. To compensate for the higher powerdensities the serial cores will either experience more throttling eventsduring an intra-migration time slice, higher migration frequencies, or adedicated local hotspot cooling solution would be required to handle theadditional thermal overhead.

There is a significant amount of research in the area of hotspotcooling. However these solutions add complexity to the overall system,and may become difficult to implement in a 3D stack where both inter-and intra-layer fluidic routing would be required. In DCM schemes, thereis parasitic computational cost associated with each throttling eventthat can become significant over time when the cycling is too rapid.Furthermore, rapid thermal cycling can lead to reduced lifetimereliability for the chip. To minimize the performance losses associatedwith these gating and throttling events, an optimized system should bedesigned that can operate for longer periods without requiring an idlefor cool-down, and have as short of an idle time as possible.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of this disclosure can be better understood with referenceto the following drawings. The components in the drawings are notnecessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the present disclosure. Moreover, in thedrawings, like reference numerals designate corresponding partsthroughout the several views.

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing(s) will be provided by the Office upon request and paymentof the necessary fee.

FIG. 1.1 illustrates an embodiment of the present disclosure.

FIG. 1.2 illustrates another embodiment of the present disclosure.

FIG. 2.1A illustrates the impact of increased thermal capacitance oncore hopping frequency and FIG. 2.2B illustrates the impact ofregenerative cooling on device utilization.

FIG. 2.2 illustrates a schematic of CTC integration in a 3D chip stack.

FIG. 2.3 illustrates a schematic of 3D computational domain and boundaryconditions.

FIG. 2.4 illustrates a schematic of an implementation where the CTC isspatially separated from the electronic device containing the hotspot.

FIG. 2.5A illustrates an optical micrograph of a test structure thatsimulates the hotspot heater in demonstrating the utility of CTCcooling.

FIG. 2.5B illustrates an optical micrograph of a CTC embodiment.

FIG. 2.6 illustrates the impact of phase change materials with differenteffective thermal conductivites (CTC devices) on transient (heating andcooling) response of the device shown in FIG. 2.4

FIG. 2.7 illustrates the impact of different CTC regeneration schemes oncooldown dynamics for CTC implementation shown in FIG. 2.4

FIG. 2.8 illustrates a summary of the achieveable cooling utilizationfactors (fraction of time when the hot spot is ON to the total CTC cycletime, including time required for CTC regeneration) for a CTC witheffective thermal conductivity of 150 W/m-K and different regenerationschemes, for the device shown in FIG. 2.4

FIG. 2.9A illustrates the experimentally observed temperature historiesof dissipating 45 W/cm² heat flux from a pulsed hotspot with CTC andwithout CTC (marked Si), demonstrating the capability of CTC tosignificantly decrease the hot spot temperature and to increase the timebefore the critical temperature (e.g., 90° C. for electronic devices) isreached.

FIG. 2.9B illustrates the experimentally observed temperature historiesof dissipating 133 W/cm² heat flux from a pulsed hotspot with CTC andwithout CTC (marked Si), demonstrating the capability of CTC tosignificantly decrease the hot spot temperature and to increase the timebefore the critical temperature (e.g., 90° C. for electronic devices) isreached.

FIG. 2.10 illustrates a time-on-a-core before reaching a 90° C.threshold for different CTC layout and material properties (forquantitative comparison, a baseline of Si only layer yields 3 ms time ofoperation before reaching a 90° C. threshold).

FIG. 2.11 illustrates the results of 3D numerical simulations for CTCperformance with and without SSC regeneration: (A) 500 W/cm² hotspotheat flux (B) 1 kW/cm².

SUMMARY

Embodiments of the present disclosure include devices or systems thatinclude a composite thermal capacitor disposed in thermal communicationwith a hot spot of the device, methods of dissipating thermal energy ina device or system, and the like.

An embodiment of a device, among others, includes: an electronic devicehaving at least one hot spot, a composite thermal capacitor disposed inthermal communication with the hot spot of the electronic device,wherein the composite thermal capacitor includes a phase changematerial, wherein the heat from the hot spot is stored by the phasechange material.

DETAILED DESCRIPTION

Before the present disclosure is described in greater detail, it is tobe understood that this disclosure is not limited to particularembodiments described, as such may, of course, vary. It is also to beunderstood that the terminology used herein is for the purpose ofdescribing particular embodiments only, and is not intended to belimiting, since the scope of the present disclosure will be limited onlyby the appended claims.

Where a range of values is provided, it is understood that eachintervening value, to the tenth of the unit of the lower limit (unlessthe context clearly dictates otherwise), between the upper and lowerlimit of that range, and any other stated or intervening value in thatstated range, is encompassed within the disclosure. The upper and lowerlimits of these smaller ranges may independently be included in thesmaller ranges and are also encompassed within the disclosure, subjectto any specifically excluded limit in the stated range. Where the statedrange includes one or both of the limits, ranges excluding either orboth of those included limits are also included in the disclosure.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. Although any methods andmaterials similar or equivalent to those described herein can also beused in the practice or testing of the present disclosure, the preferredmethods and materials are now described.

All publications and patents cited in this specification are hereinincorporated by reference as if each individual publication or patentwere specifically and individually indicated to be incorporated byreference and are incorporated herein by reference to disclose anddescribe the methods and/or materials in connection with which thepublications are cited. The citation of any publication is for itsdisclosure prior to the filing date and should not be construed as anadmission that the present disclosure is not entitled to antedate suchpublication by virtue of prior disclosure. Further, the dates ofpublication provided could be different from the actual publicationdates that may need to be independently confirmed.

As will be apparent to those of skill in the art upon reading thisdisclosure, each of the individual embodiments described and illustratedherein has discrete components and features which may be readilyseparated from or combined with the features of any of the other severalembodiments without departing from the scope or spirit of the presentdisclosure. Any recited method can be carried out in the order of eventsrecited or in any other order that is logically possible.

Embodiments of the present disclosure will employ, unless otherwiseindicated, techniques of physics, thermodynamics, heat transfer,chemistry, material science, and the like, which are within the skill ofthe art. Such techniques are explained fully in the literature.

The following examples are put forth so as to provide those of ordinaryskill in the art with a complete disclosure and description of how toperform the methods and use the compositions and compounds disclosed andclaimed herein. Efforts have been made to ensure accuracy with respectto numbers (e.g., amounts, temperature, etc.), but some errors anddeviations should be accounted for. Unless indicated otherwise, partsare parts by weight, temperature is in ° C., and pressure is inatmosphere. Standard temperature and pressure are defined as 25° C. and1 atmosphere.

Before the embodiments of the present disclosure are described indetail, it is to be understood that, unless otherwise indicated, thepresent disclosure is not limited to particular materials, reagents,reaction materials, manufacturing processes, or the like, as such canvary. It is also to be understood that the terminology used herein isfor purposes of describing particular embodiments only, and is notintended to be limiting. It is also possible in the present disclosurethat steps can be executed in different sequence where this is logicallypossible.

It must be noted that, as used in the specification and the appendedclaims, the singular forms “a,” “an,” and “the” include plural referentsunless the context clearly dictates otherwise. Thus, for example,reference to “a support” includes a plurality of supports. In thisspecification and in the claims that follow, reference will be made to anumber of terms that shall be defined to have the following meaningsunless a contrary intention is apparent.

As used herein, the term “adjacent” refers to the relative position ofone or more features or structure, where such relative position canrefer to being near or adjoining. Adjacent structures can be spacedapart from one another or can be in actual contact with one another. Insome instances, adjacent structures can be coupled to one another or canbe formed integrally with one another.

Discussion

Embodiments of the present disclosure include devices or systems thatinclude a composite thermal capacitor disposed in thermal communicationwith a hot spot of the device, methods of dissipating thermal energy ina device or system, and the like. The composite thermal capacitor is inthermal communication (e.g., exchange heat) with one or more hot spotsin the device. In an embodiment, the composite thermal capacitorstructure functions to remove, dissipate, store and/or spread heat, froma hot spot in the device, which results in a large increase in the localthermal capacitance and allows the device to operate for longer periodsof time. In an embodiment, the composite thermal capacitor cantemporarily store thermal energy from hard-to-access areas of atwo-dimensional core architecture or a three-dimensional stack corearchitecture. The composite thermal capacitor can be used to maximizethermal capacitance in high power areas, minimizing hopping and/orthrottling frequency in dynamic core migration strategies. Theseimprovements can result in the reduction of the parasitic computationaloverhead associated with dynamic core migration strategies. Asymmetriccooling and/or regeneration of the composite thermal capacitor can beused to maximize overall core utilization (the fraction of time during adefined period where an electronic device is able to actively function,e.g., perform computations) in dynamic core migration strategies.Because the time response of the composite thermal capacitor (CTC)matches an electronic device's thermal capacitance time scale due to itsintrinsic dynamics of power dissipation, it can “homogenize” the thermaltime scales of electronic devices with very different power dissipationprofiles. With time scales levelized across the chip, thread andworkload scheduling becomes significantly simplified for dynamicallyoperated devices.

FIG. 1.1 illustrates an embodiment of a device 10 of the presentdisclosure, while FIG. 1.2 illustrates another embodiment of the device20 of the present disclosure. The device 10 includes an electronicdevice 12 having at least one hot spot and a composite thermal capacitor14 disposed in thermal communication with the hot spot of the electronicdevice 12. The composite thermal capacitor 14 includes a phase changematerial, where the thermal energy from the hot spot is stored by thephase change material.

The device 20 in FIG. 1.2 is similar to device 10 in FIG. 1.1 but alsoincludes an active regeneration cooling device 16 in thermalcommunication with the composite thermal capacitor 14. An external heatsink 18 is in thermal communication with the active regeneration coolingdevice 16. The electronic device 12 includes at least one hot spot andthe composite thermal capacitor 14 is in thermal communication with theelectronic device 12 to store thermal energy from the hot spot. As indevice 10 in FIG. 1.1, the composite thermal capacitor 14 includes aphase change material, where the thermal energy from the hot spot isstored by the phase change material. The active regeneration coolingdevice 16 dissipates thermal energy from the composite thermal capacitor14. The external heat sink 18 dissipates thermal energy from the activeregeneration cooling device 16. Thus, thermal energy can be removed fromthe hot spot through the composite thermal capacitor 14, to the activeregeneration cooling device 16, and to the external heat sink 18.

In device 10 and 20, the electronic device 12 and the composite thermalcapacitor 14 can be adjacent one another. In an embodiment, theelectronic device 12 and the composite thermal capacitor 14 can be indirect contact with one another. In another embodiment, the electronicdevice 12 and the composite thermal capacitor 14 can be indirectlyconnected using a structure such as a network of high conductivitythermal vias or a slab heat spreader, a heat pipe, a fluidic loop, solidstate heat pump, or any other intermediate cooling/heat transfer devicesor a combination thereof.

In device 20, the composite thermal capacitor 14 and the activeregeneration cooling device 16 can be adjacent one another. In anembodiment, the composite thermal capacitor 14 and the activeregeneration cooling device 16 can be in direct contact with oneanother. In another embodiment, the composite thermal capacitor 14 andthe active regeneration cooling device 16 can be indirectly connectedusing a structure such as a network of high conductivity thermal vias ora slab heat spreader, a heat pipe, a fluidic loop, solid state heatpump, or any other intermediate cooling/heat transfer devices or acombination thereof.

In device 20, the active regeneration cooling device 16 and the externalheat sink 18 can be adjacent one another. In an embodiment, the activeregeneration cooling device 16 and the external heat sink 18 can be indirect contact with one another. In another embodiment, the activeregeneration cooling device 16 and the external heat sink 18 can beindirectly connected using a structure such as a network of highconductivity thermal vias or a slab heat spreader, a heat pipe, afluidic loop, solid state heat pump, or any other intermediatecooling/heat transfer devices or a combination thereof.

In an embodiment, the device 10 can include a computer chip, anelectronic component, a display, an engine, a fuel cell or other powergeneration device (e.g., solar cell), a chemical reactor, a lightsource, and the like. In particular, the device 10 can include amicroprocessor, Application Specific Integrated Circuits (ASICs),System-on-a-Chip (SoC), a microelectronic chip, a optoelectronic chip, ahybrid optoelectronic/microelectronic chip, a memory device, analog orradio frequency (RF) micro devices, System on a Package (SOP), biochips,medical or electronic imaging devices, and on chip power managementdevices such as AC/DC converters.

In an embodiment, the electronic device 12 can be a portion or featureof the device 10. In an embodiment, the electronic device includes atwo-dimensional semiconductor chip stack, a three-dimensionalsemiconductor chip stack, a multi-core semiconductor chip, ApplicationSpecific Integrated Circuits (ASICs), System-on-a-Chip (SoC), amicroelectronic chip, a memory device, a optoelectronic chip, a hybridoptoelectronic/microelectronic chip, analog or radio frequency (RF)micro devices, System on a Package (SOP), biochips, medical orelectronic imaging devices, and on chip power management devices such asAC/DC converters.

Phase change materials have unique thermophysical properties in thatthey can absorb thermal energy without temperature rise during themelting process and are capable of storing and releasing large amountsof thermal energy. Once a state change occurs (e.g., solid changes to aliquid), heat is released or absorbed. Thermal energy from the hot spotcan be thermally communicated with the phase change material by placingthe phase change material adjacent the hot spot in the electronicdevice. The thermal energy of the phase change material can be thermallycommunicated to a fluid or air or to another structure in thermalcommunication with the composite thermal capacitor.

The phase change material can be a solid-to-solid, a solid-to-liquid, asolid-to-gas, or a liquid-to-gas, phase change material. The types ofphase change material can include materials that can undergo any ofsolid-to-solid, a solid-to-liquid, a solid-to-gas, or a liquid-to-gas,phase changes. In an embodiment, the phase change material is areversible phase change material. In an embodiment, the phase changematerial can be organic, inorganic, a eutectic alloy, an alloy, or acombination thereof. The phase change material can include indium (e.g.,indium acetate is a precursor material), tin (e.g., tin acetate is aprecursor material), lead (e.g., lead acetate is a precursor material),bismuth (e.g., bismuth acetate is a precursor material), gold, silver,salt (NaCl, etc), paraffin wax, and other organic materials can also beused. Eutectic alloys that can be used include Ag (silver), Al(aluminum), Au (gold), Bi (bismuth), Cu (copper), In (indium), Ni(nickel), Pb (lead), Sb (antimony), Sn (tin), Zn (zinc), Cd (cadmium),(Ga) Gallium and other elements. Alloys that can be used include abinary, ternary, or other higher order alloys of the elements that canfrom alloys. Solid-to-solid phase change materials can include polymericsolids with multiple defined crystalline or amorphous solid states. Thephase change materials can be modified with chemical components thatwould improve their wetting characteristics to effectively fill thecavity of the composite thermal capacitance.

In an embodiment, the composite thermal capacitor 14 including the phasechange material can have a height of about 10 nm to 1 cm or about 5 μmto 5 mm, a length of about 5 μm to 10 cm or about 100 μm to 1 mm, and awidth of about 5 μm to 10 cm or about 100 μm to 1 mm.

In an embodiment, the composite thermal capacitor can also include ahigh thermal conductivity material. The high thermal conductivitymaterial can be included to assist in the heat dissipation from thephase change material to the fluid or air or another structure inthermal communication with the composite thermal capacitor. Also, thehigh thermal conductivity material can be included to promote lateraland vertical (i.e., across the PCM layer) heat spreading within thecomposite thermal capacitor for improved utilization of the phase-changematerial for heat storage. In an embodiment, the high thermalconductivity material can be mixed with the phase change material and/orbe disposed in an area (second area) distinct from the phase changematerial (first area) but in thermal communication with the phase changematerial. The first area including the phase change material can have across-section such as a polygonal cross-section, a circularcross-section, substantially circular cross-section, annular crosssection, and a combination thereof. The second area including the highthermal conductivity material is the area on the outside or insideboundary of the first area. The areas are designed to efficientlythermally communicate heat energy from the phase change material to thehigh thermal conductivity material to a material or structure (See FIG.1.2, an active regeneration cooling device) in thermal communicationwith the composite thermal capacitor.

In an embodiment, the high thermal conductivity material can includecopper, silver, gold, aluminum, graphitized carbon, silicon, diamond,carbon nanotubes, graphene or a combination thereof.

In an embodiment, the composite thermal capacitor 14 including the phasechange material and the high thermal conductivity material can have aheight of about 10 nm to 1 cm or about 1 μm to 1 mm, and a width ofabout 1 μm to 10 cm or about 100 μm to 1 mm.

In an embodiment, the ratio of the phase change material to the highthermal conductivity material in the composite thermal capacitor isabout 1:100 to 1;1.

In an embodiment, the composite thermal capacitor is in thermalcommunication with the hot spot of the electronic device using one ormore through-silicon vias. The vias can be made of materials such ascopper, silver, gold, aluminum, graphitized carbon, diamond, carbonnanotube, graphene, and a combination thereof. The vias can have aheight of about 10 nm to 2 cm or about 5 μm to 5 mm a length of about 5nm to 1 mm or about 1 μm to 100 μm, and a width of about 5 nm to 1 mm orabout 1 μm to 100 μM.

In an embodiment, the active regeneration cooling device removes thermalenergy from the composite thermal capacitor. In an embodiment, theactive regeneration cooling device can include a fluidic cooling device,such as an array of jets, fluidic channels with or without surfaceenhancements such plates, fins, pins, wings or dimples, spray coolers,pool boiling or evaporation devices and combinations thereof. In anembodiment, the active regeneration cooling device can include a solidstate cooling device such as a thin film thermoelectric, superlattice,bulk thermoelectric, or thermionic coolers, and a combination thereof.

In an embodiment, the external heat sink removes thermal energy from theactive regeneration cooling device. In another embodiment, the externalheat sink removes thermal energy from the composite thermal capacitor.The external heat sink can have various shapes (e.g., a polygonalcross-section) and can included fins, pin-fin arrays, or other surfacesextending from the base of the external heat sink to increase thesurface area of the heat sink. The external heat sink can be made ofsolid or porous materials (preferably with high thermal conductivity)such as, but not limited to, copper, aluminum, silicon, diamond, steel,carbon, different polymers, or composite materials, and combinationsthereof.

EXAMPLE

Brief Introduction

While 3D stacked multi-processor technology offers the potential forsignificant computing advantages, these architectures also face with thesignificant challenge of small, localized hotspots with very large powerdissipation due to the placement of asymmetric cores, heterogeneousdevices and performance driven layouts. In this Example, a new thermalmanagement solution is proposed that seeks to maximize the performanceof microprocessors with dynamically managed power profiles. To mitigatethe non-uniformities in chip temperature profiles resulting from thedynamic power maps, phase change materials (PCMs) with an embedded heatspreader network are strategically positioned near localized hotspots,resulting in a large increase in the local thermal capacitance in theseproblematic areas. We show that this results in an up-to-twenty-foldincrease in the time that a thermally constrained core can operatebefore a power gating or core migration event is required.

Coupled to the PCMs are solid state coolers (SSCs) that serve as a meansfor fast regeneration of the PCMs during the cool down periodsassociated with throttling events. Using this combined PCM/SSC approachallows for devices that operate with desirable combination of lowthrottling frequency and large overall core duty cycles, thus maximizingcomputational throughput.

Discussion

In order to address the unique challenges associated with thermalnon-uniformities in 3D many-core architectures, we propose a solutionthat is a departure from the traditional approach of bringing aspecialized liquid cooling device to the hotspot to locally enhance heattransfer. Instead of attempting to increase the heat transfercoefficients in the hard-to-access internal layers of a 3D stack, thedesign proposed in this work seeks to locally increase the thermalcapacitance in thermally troublesome areas of the chip to maximize thetime that a core or device can operate before reaching its thermalthreshold.

As shown schematically in FIG. 1.1A, for dynamically operated microarchitectures, increasing the thermal capacitance of a device cansignificantly decrease the frequency of core hopping, gating, orthrottling events. This in turn reduces the parasitic computationaloverhead associated with the DCM implementation. Thus, matching adevice's thermal capacitance to its intrinsic dynamics of powerdissipation can “homogenize” the thermal time scales of devices withvery different power dissipation profiles.

In order to locally alter the dynamic thermal properties of the devices,a portion of the silicon on the inactive back side of the chips can beetched away and a material with a higher thermal capacitance, forexample phase change materials (PCMs), can be placed in the cavitycreated by removal of silicon (FIG. 2.2). The PCMs, named because oftheir ability to reversibly melt/solidify during heating/coolingprocesses, can absorb a large amount of thermal energy at a relativelyconstant temperature. One challenge of utilizing PCMs is that theirtypically low thermal conductivities (κ) limit the amount of materialthat can be melted prior to the device reaching its thresholdtemperature. This can be mitigated by using a “composite thermalcapacitor” (CTC), consisting of PCM incorporated into a high thermalconductivity matrix to enhance heat spreading and therefore improve PCMutilization.

While the addition of phase change materials may extend the operatingtimes of dynamically operated devices, some portion of each duty cyclewhere the device is idled or throttled will inevitably need to beallocated to allow the device to cool before beginning the next cycle.Because the CTC stores a tremendous amount of energy during the meltingprocess, a system with CTC enhancements alone may have relatively longintrinsic cool-down times. Recognizing this potential drawback, athoughtfully designed thermal solution must be designed with a means torapidly regenerate the CTC, maximizing the device's availability, andthus overall performance (FIG. 2.1B).

Solid-state coolers (SSC's), such as thin film thermoelectric orsuperlattice coolers, are attractive candidates for PCM regeneration, asthey are capable of moving very large heat fluxes, as long as minimalsub-cooling is required [16]. In 3D architectures, an added benefit ofSSC's comes from the ability to establish physical separation betweenthe cooled and heated junctions through careful placement of the anodeand cathode [17]. Thus the cooled anode can be located within the 3Dstack near the CTC to assist in the regeneration of the CTC, while theheated cathode can be placed closer to the external heat sink where itcan more readily reject the generated heat to the ambient. Because ofthe nature of the melting and solidification process, little sub-coolingis required to regenerate the CTC, so that the SSC instead acts as asort of thermal fast lane, increasing the rate at which the thermalenergy from the CTC travels to the heat sink over spreading andconduction through the stack alone.

While there is certainly application space for the significant researchinto using SSCs as standalone hotspot cooling devices, for example[16-18]. The standalone SSC's heat dissipation capacity is highlydependent on the hotspot size[16], and it must have a cold junction invery close physical proximity to the heat source to be effective [18].The CTC relaxes those constraints, because it is the CTC that is inclose contact with the hotspot directly absorbing the heat load, and theSSC acts only as a secondary thermal transport enhancer with no directeffect on the maximum temperatures the device experiences. Furthermore,because the SSC only operates during the regeneration portion of theoperating cycle, the power consumption of the SSC is less of a concernthan if it were operating continually as a primary cooling device.

Method

2D Model-CTC Limiting Performance

To evaluate the potential of this approach we have modeled theperformance of a CTC that uses an azimuthal array of diamond shapedloops of either Cu or CVD diamond as a heat spreader matrix (FIG. 2.4).The voids between the loops are filled with a PCM with properties of aBi—In—Sn alloy with a 60° C. melting temperature. To simulate theprocess of activating a high power core and storing the energy in thePCM the heat equation is solved within a planar (thickness-averaged) CTCcomputational domain with the dimensions shown in FIG. 2.4. The impactof the melting of the PCM is accounted for by incorporating a modifiedenthalpy term in the heat equation, ∂(ρH)/∂t=∇·(K∇T)+Ė_(g), as describedin [19]. The source term Ė_(g), accounts for the heat generation at thehotspot, assumed to be uniformly distributed in the vertical (across theCTC layer) direction. In practice, the heat generation only occurs in athin layer on the active side of the chip, so this approximation is onlyvalid in the limit of thin PCM layers with high effective thermalconductivity across the plane, such that temperature gradients in thevertical direction are negligible.

The outer boundaries of the computational domain are consideredadiabatic, and the heat generation in the hotspot domain is taken as 33W/mm³ corresponding to a 500 W/cm² hotspot under a 150 μm thick CTC, inline with projected peak heat fluxes in future devices [10]. The size ofthe regular octagonal domain is set at a 3 mm circumdiameter to ensurethat the CTC does not monopolize an impractical amount of valuable realestate in the bulk Si, which is also needed for through-layerinterconnect routing [20]. For each configuration analyzed, the chipsstarts at an initially uniform temperature of 59° C. and the simulationsare run until the junction temperature reaches 90° C.

Because of the major assumptions included in this model, includingcomplete isolation from any external heat sink, neglecting temperaturegradients in the vertical direction, and large allowable temperatureswings (up to 30° C.), this initial analysis should give a good pictureof what best case potential operating time enhancements can be achievedwith the CTC design.

3D Model-CTC Integrated into a 3 Layer Stack with SSC Regeneration.

After considering the potential of various PCM-high k spreaderconfigurations in the 2D domain, a fully three-dimensional model, shownin FIG. 2.3, was built to investigate how the CTC with SSC regenerationwould perform when packaged in a configuration similar to what would beexperienced in an actual multi-layer stack. The computational domainconsists of three 1.5 cm×1.5 cm×150 μm silicon tiers with a 20 μm thickpolymer between each layer, as a bonding agent. In each 20 μm polymerlayer a 5×10¹⁰ W/m³ source term is applied, to simulate the 100 W/cm²background heat flux of the layer. At the bottom surface of the lowestlayer, a 100 W/cm² background heat flux is applied as well, except for a1 mm×1 mm square area at the center where the hotspot is simulated. Thehotspot is taken to have a heat flux (either 500 W/cm² or 1 W/cm²)applied until the temperature rises by 11° C., when the boundarycondition is changed to adiabatic, to simulate completely shutting thecore down during the cool down portion of the cycle.

Directly above the hotspot, a 3 mm×3 mm portion of the silicon in thebottom silicon tier has been replaced with a CTC with the estimatedproperties of a Bi—In—Sn alloy with 79° C. melting temperature(alloy-174), with an enhanced effective thermal conductivity rangingfrom 40-120 W/m−K by embedding the high thermal conductivity matrix(e.g., copper or diamond). Above the CTC is a 3 μm thick SSC with theproperties of SiGe which can optionally be activated to enhance theregeneration during the cool down portion of the cycle. To simulate theSSC operation, additional source terms are included into a heat transfermodel of the device. Some source terms model the Peltier effect at theanode metal-SiGe, SiGe-silicon, and silicon-cathode metal interfacesaccording to: Ė_(g)=I(S_(i)−S_(j))T [16], where I is the supply currentto the device, S_(i) is the Seebeck coefficient of the i^(th) material(i.e. metal, SiGe, etc), and T is the temperature of the interface. Theother source terms account for Joule heating in the SSC, siliconsubstrate, and the vertical silicon via that electrically connects thesubstrate to the cathode at the top (heat sink adjacent) layer. Jouleheating is computed from Ė_(g-joule)=1²R, where the resistance R is thesum of the one-dimensional conduction resistance R_(1D)=t/σA, theelectrical spreading resistance R_(spr)=8/3π²σr and an Ohmic contactresistance of 10⁻⁶ Ωcm² [21]. In these expressions, t is the thicknessof the layer, s is the electrical conductivity of the material, A is thecross sectional area of the layer, and r is the effective radius of thecontact area where spreading occurs.

At the top of the third layer a convective boundary condition is appliedwith an ambient temperature of 27° C. (300 K) and an effective heattransfer coefficient of 87,000, which is equivalent to a heat sink witha thermal resistance of 0.05 K/W.

Alternate Configurations

As described in the Discussion section an alternate embodiment of thedevice can have the CTC physically separated from the electronic devicecontaining the hotspot, with thermal communication established via athermally conductive slab or via or through conduction throughadditional intermediate heat transfer devices. An example of this typeof configuration is shown in FIG. 2.4. Here the electronic devicecontaining the hotspot is embedded in a 3D stack with fluidic channelsin between each layer to remove the background heat fluxes from thedevices. The hotspot in the bottom layer of the stack cannot beadequately cooled by the background cooling, so a CTC is needed to bringits thermal time response in line with the rest of the devices in thestack.

In this configuration the CTC is placed several layers above the hotspotto allow for the placement of the fluidic channels in the intermediatelayers. Thermal communication is established using copper though siliconvias (TSV's) as well as through conduction through the silicon from thevertically adjacent electronic devices.

As was done in the previous 3D modeling discussed above CTCimplementations of varying thermal conductivity were considered todetermine their effectiveness in increasing the device's availability.The effective of changing the method of active regeneration scheme wasalso considered here. In addition to the use of a solid state cooler,the effects of using varying types of fluidic cooling were considered.The effects of increasing the heat transfer coefficient of the fluidiccooling scheme from 22 kW/m²−K to 100 kW/m²−K (baseline vs. enhancedrate regeneration) were considered. In addition the effects on theregeneration rate of sub cooling the coolant 10 K from 310 K to 300 Kwere considered.

Experimental Characterization

A prototype including a hotspot heater and silicon CTC device has beenfabricated and characterized to validate the potential of the CTCconcept for enhancing device operating times. The 1 mm×1 mm squarehotspot heater, shown in FIG. 2.5, was fabricated on a Pyrex wafer tominimize spreading in the substrate, instead concentrating heating inthe vicinity CTC under investigation. The prototype CTC was fabricatedby etching diamond shaped troughs in a 190 μm thick Si wafer that wascoated with a 1 μm thick layer of Pt with Ti adhesion layer to improvewetting of the Si spreader by the PCM. The troughs were filled withalloy 136, a eutectic alloy of 49% Bi, 21% In, 18% Pb, 12% Sn with a 58°C. melting temperature.

The CTC was attached to the hotspot using a Ceramique, spreadablethermal interface material (TIM) and the entire device was thenpreheated in a 53° C. oven to simulate the hot conditions that might beexperienced inside of a 3D stack. The hotspots were then activated forshort pulses of either 100 ms at ˜133 W/cm² or 30 ms at ˜45 W/cm^(2.)

Results

As shown in FIG. 2.4, there is a significant potential for extending thecore operating time before throttling/hopping is required with the useof CTC. When compared with the baseline case of pure Si heat spreadingthrough the device stack, which allows the core to operate for about 3ms before reaching the threshold temperature, an increase in operatingtime ranging from a factor of 10× for the copper-based matrix up to over20× for the diamond-based matrix can be achieved.

Two separate peaks are seen in FIG. 2.10. The first local maximum occursin the regime where the PCM fraction is above 90% and the performance islimited by the tradeoff between the increased spreading that is achievedwith adding additional high κ materials and the associated decrease inthe amount of PCM available for heat storage. With higher κ materialssuch as diamond, CNTs or graphene, an appreciable increase in spreadingcan be achieved with the addition of a relatively small amount of thehigher κ material, so that the capacitive properties of the compositestill closely resemble that of the unaltered PCM. However, with moremoderate κ spreading materials such as copper or silicon, the increasein spreading at very high PCM loading is small, diminishing themagnitude of the first peak.

In the second maximum, which occurs at PCM loadings below 60%, theperformance is limited primarily by the amount of lateral crosssectional area allotted to the CTC. In this regime, additional spreadingcould potentially be achieved by adding extra high κ materials, but thearea that is made available for the placement of the CTC is limited to 3mm in diameter by the electrical design and routing constraintsdiscussed above. While the performance of both regimes is governed bythe combination of the energy storage due to phase change at the meltfront and single phase heating of the composite material in the regionswhere melting has already occurred, in this lower PCM loading regime thesingle phase portion of the capacitance is strongly affected by thepresence of the higher κ materials.

In practice, in an actual device the entire 3 mm diameter may not berequired, as replacing the Si with the CTC only makes sense in theregions where melting occurs before reaching the threshold temperature.The presence of the extra CTC materials in the simulations where theywere ultimately not needed does affect the accuracy of the resultshowever, because the regions beyond the melt front remain effectivelyadiabatic throughout the transient.

The results of the 3D simulations (FIG. 2.11) show that the potential ofthe CTC to maximize device operating times when packaged into arealistic device remain significant. For the configuration considered,operating time enhancements of over 4× can be achieved at 500 W/cm², andover 10× is possible at 1 kW/cm². Notably, at 1 kW/cm² the operatingtime is increased from 0.7 ms up to 7.5 ms, which would bring thehottest cores in line with the time constant of the rest of the chip[9], significantly simplifying the task scheduling process.

When relying on spreading in the bulk alone for regenerating the PCM,the device's overall availability becomes low, which could beproblematic if there is not sufficient device redundancy on the chip.The implementation of active SSC regeneration significantly decreasesthe unavailability problem, reducing device idle time requirements by2×-3×. While the SSC regeneration significantly improves performance ofCTC, overall availability of the core with CTC still trails theunaltered Si values for this configuration.

In the alternate configuration an over 100 ms increase in amount of timethat the hotspot device can operate before requiring a throttling eventcan be achieved with the use of a CTC with an effective thermalconductivity of 150 W/m−K, shown in FIG. 2.6. Regarding the regenerationschemes, FIG. 2.7 shows that increases in overall utilization of up to38% can be achieved depending on the regeneration scheme. The resultsfor each case are summarized in FIG. 2.8. Sub cooling provides anadditional 4.5% cooling over the baseline fluidic regeneration, whileenhancing the regeneration rate or using a solid state cooler canprovide much larger increases in overall device utilization.

As seen in FIG. 2.9, the experimental results show that in each casesome improvement of the thermal response of the hotspot was observedwhen the CTC was placed on top of the heater when compared to theresponse observed when the CTC was replaced with an unaltered piece of190 μm thick Si. For example, in the 45 W/cm² case, increases inoperating time before throttling in the range of ˜4.5×-6× can beachieved for allowable temperature fluctuations of <10° C. In the 133W/cm² case if an 85° C. maximum allowable junction temperature throttlecriteria is applied an increase in operating time of ˜4.4× can beachieved.

CONCLUSION

We have introduced a new thermal management approach based on animbedded CTC network that can be applied to dynamically operatedmicroprocessors experiencing non-uniformities in their power profilesdue to asymmetric architectures or integration of heterogeneous devices.It has been shown that with careful design this approach can have adramatic impact on core hopping and throttling frequencies, resulting indevices with greater spatial and temporal synchronization. One of themost important advantages of the approach is that it is locally passive,requiring no additional fluidic routing to realize its benefits.

The addition of SSC regeneration dramatically increases the systemavailability over what can be achieved with the CTC alone, althoughstill falling short of the availability that would be seen with theunaltered silicon substrate. Further optimization of the SSC parametersand properties could close this gap however, as well as consideration ofnon-idealities such as anisotropy in the interface layer thermalconductivities, smaller allowable temperature swings and less aggressiveheat sink thermal resistances. Even with the current configuration, theproposed solution allows the chip designer to consider these tradeoffsof significantly reduced throttling frequency against a small loss inoverall availability to produce a system that most closely meets thespecific performance requirements for a given application.

REFERENCES Each of which is Included Herein by Reference

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It should be noted that ratios, concentrations, amounts, and othernumerical data may be expressed herein in a range format. It is to beunderstood that such a range format is used for convenience and brevity,and thus, should be interpreted in a flexible manner to include not onlythe numerical values explicitly recited as the limits of the range, butalso to include all the individual numerical values or sub-rangesencompassed within that range as if each numerical value and sub-rangeis explicitly recited. To illustrate, a concentration range of “about0.1% to about 5%” should be interpreted to include not only theexplicitly recited concentration of about 0.1 wt % to about 5 wt %, butalso include individual concentrations (e.g., 1%, 2%, 3%, and 4%) andthe sub-ranges (e.g., 0.5%, 1.1%, 2.2%, 3.3%, and 4.4%) within theindicated range. In an embodiment, the term “about” can includetraditional rounding according to significant figures of the numericalvalue. In addition, the phrase “about ‘x’ to ‘y’” includes “about ‘x’ toabout ‘y”’.

Many variations and modifications may be made to the above-describedembodiments. All such modifications and variations are intended to beincluded herein within the scope of this disclosure and protected by thefollowing claims.

Therefore, the following is claimed:
 1. A device, comprising: anelectronic device having at least one hot spot, and a composite thermalcapacitor disposed in thermal communication with the hot spot of theelectronic device, wherein the composite thermal capacitor includes aphase change material, wherein the heat from the hot spot is stored bythe phase change material.
 2. The device of claim 1, wherein the phasechange material is selected from the group consisting of:solid-to-solid, a solid-to-liquid, a solid-to-gas, and a liquid-to-gas,phase change material.
 3. The device of claim 1, wherein the compositethermal capacitor includes the phase change material imbedded into amatrix of a high thermal conductivity material.
 4. The device of claim3, wherein the high thermal conductivity material is selected from thegroup consisting of: copper, silver, gold, aluminum, graphitzed carbon,silicon, carbon nanotubes, diamond, graphene, and a combination thereof.5. The device of claim 3, wherein the ratio of the phase change materialto the high thermal conductivity material is about 1:100 to 1:1.
 6. Thedevice of claim 1, wherein the electronic device is selected from thegroup consisting of: a two-dimensional semiconductor chip stack, athree-dimensional semiconductor chip stack, a multi-core semiconductorchip, a memory device, Application Specific Integrated Circuits (ASICs),System-on-a-Chip (SoC), a microelectronic chip, a optoelectronic chip, ahybrid optoelectronic/microelectronic chip, a memory device, analog orradio frequency (RF) micro devices, System on a Package (SOP), biochips,medical or electronic imaging devices, and on chip power managementdevices.
 7. The device of claim 1, wherein the composite thermalcapacitor is in thermal communication with the hot spot of theelectronic device using a structure selected from the group consistingof one or more through-silica vias, a high conductivity slab, a heatpipe, a fluidic loop, a solid state heat pump, an intermediateelectronic device, and a combination thereof.
 8. The device of claim 1,further comprising an active regeneration cooling device in thermalcommunication with the composite thermal capacitor, wherein the heatfrom the composite thermal capacitor is dissipated by the activeregeneration cooling device.
 9. The device of claim 8, wherein theactive regeneration cooling device is selected from the group consistingof: solid state cooling device, a fluidic cooling device, a heat pipe,and a combination thereof.
 10. The device of claim 8, further comprisingan external heat sink in thermal communication with the activeregeneration device.
 11. The device of claim 3, wherein the compositethermal capacitor has a first area and a second area, wherein the firstarea includes the phase change material and the second area includes thehigh thermal conductivity material, wherein the first area can includeone or more portions, wherein each portion has the second area as aboundary, and the first area and second area are in thermalcommunication between each other.
 12. The device of claim 11, whereineach portion of the first area has a cross-section selected from thegroup consisting of: a polygonal cross-section, a circularcross-section, substantially circular cross-section, annular crosssection, and a combination thereof.
 13. The device of claim 12, whereineach portion has an outer boundary defined by the second area.